1. Field of the Invention
This invention generally relates to a circuit and a method for calibrating a data control signal, and more particularly, to a circuit and a method for calibrating a data control signal of a DRAM memory.
2. Description of the Related Art
FIG. 1 shows a schematic view of a conventional memory controller 10 coupled to a double data rate (DDR) memory 12. The memory controller 10 utilizes a bi-directional data strobe signal DQS to write a data signal DQ into the DDR memory 12 or read the data signal DQ from the DDR memory 12. During writing operations, the memory controller 10 transmits the data strobe signal DQS and the data signal DQ to the DDR memory 12. In addition, during reading operations, the DDR memory 12 transmits the data strobe signal DQS and the data signal DQ to the memory controller 10.
According to DDR memory standard, the memory controller 10 and the DDR memory 12 sample data contained in the data signal DQ by each rising edge and each falling edge of the data strobe signal DQS. Therefore, it is relatively significant for the validity of the sampled data that the data strobe signal DQS is matched with the data signal DQ.
In the memory controller 10 or the DDR memory 12, the data strobe signal DQS can be outputted by an output driving circuit 14 as shown in FIG. 2. The output driving circuit 14 has at least one PMOS transistor 14a, one NMOS transistor 14b and an output terminal 15 for outputting the data strobe signal DQS. When the PMOS transistor 14a and the NMOS transistor 14b have the same driving ability, the output terminal 15 will output a data strobe signal DQS, as shown in FIG. 3, of which the rising time tr and the falling time tf are equal. However, due to the differences resulting from the manufacturing processes for the PMOS transistor 14a and the NMOS transistor 14b, they generally have different driving abilities such that the rising time tr and the falling time tf of the data strobe signal DQS are unequal. For example, if the driving ability of the PMOS transistor 14a is weaker than that of the NMOS transistor 14b, the rising time tr will be longer than the falling time tf. On the contrary, if the driving ability of the PMOS transistor 14a is stronger than that of the NMOS transistor 14b, the rising time tr will be shorter than the falling time tf.
Similarly, since the data signal DQ is also outputted by an output driving circuit, which is the same with the output driving circuit 14 shown in FIG. 2, the rising time and the falling time of the data signal DQ are also unequal.
In general, when the PMOS transistor and the NMOS transistor do not match (i.e. having different driving abilities), the skew between the data strobe signal DQS and the data signal DQ (i.e. DQ-DQS skew) is the smallest if both transition edges of the data strobe signal DQS and the data signal DQ are rising edges or falling edges at the same time. On the contrary, the skew between the data strobe signal DQS and the data signal DQ (i.e. DQ-DQS skew) is the largest if the transition edge of the data strobe signal DQS is opposite to the transition edge of the data signal DQ at the same time, meaning that one is a rising edge while the other is a falling edge. Taking FIG. 4 for example, if the PMOS transistor and the NMOS transistor do not match with each other to cause the rising time to be shorter than the falling time in the data strobe signal DQS and the data signal DQ, the DQ-DQS skew is the smallest during the time interval from t1 to t2 and the largest during the time interval from t3 to t4. Therefore, the DQ-DQS skew during the time interval from t3 to t4 will limit the valid time interval for sampling the required data.